Concept Engineering suit  7.1.4

StarVision PRO 7.0 represents the state-of-the-art in debug solutions for advanced electronic SoCs. The incorporation of Concept’s leading visualization and detection technology enables rapid cause-effect analysis for efficient functional analysis. This advanced and unique mixed-mode debug platform seamlessly combines SPICE and transistor analysis from our market leading SpiceVision PRO tool with digital RTL and gates from our advanced RTLvision PRO tool. It is fully customizable and incorporates many advanced features not available in other debug solutions, to handle the most complex of SoC platforms.
 

• Powerful general-purpose debugger for rapid cause-effect resolution
• Effective mixed-mode, RTL, Gate, SPICE and post-layout level debug
• Customizable tool platform with specialized SoC & IP capabilities

RTLvision PRO 7.0 simplifies the visualization of large RTL designs, including third party IP and reused blocks. Using Concept’s award winning visualization technology, the tool provides the unique and effective graphical rendering of RTL code structures, allowing engineers to quickly appreciate design functionality. Supporting SystemVerilog, VHDL and Verilog, RTLvision PRO comes complete with a range of debug views such as a powerful waveform display, an interactive cone of influence window, and other displays for a complete, 360° picture of the device.

• Mixed-HDL IP comprehension using Concept’s unique, leading RTL visualization approach, makes complex SoC functionality crystal clear
• Advanced debug options, including waveform signal analysis, interactive logic cone and other specialized views, allow efficient bug eradication
• Specialized SoC tools such as clock tree analysis, as well as custom feature inclusion and auto-documentation increases tool ease-of-use

GateVision PRO 7.0 is the third generation of graphical, gate-level netlist analyzers and viewers from Concept Engineering. Completely rewritten to run on modern 64bit platforms to handle the largest designs and SoCs, GateVision PRO provides a range of powerful debug and comprehension capabilities. These include intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation.


SpiceVision PRO 7.0 takes SPICE netlists and models and generates clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, debug, and optimization at the transistor-level.
SPICE circuits and models are the common currency of the EDA world. They are generated by many EDA tools and provide a description of the circuit at the lowest component abstraction level, the transistors, capacitors, resistors and even the interconnect that make up an IC or IP components. But for all but the most of trivial designs, SPICE files are very difficult to read and understand. SpiceVision PRO automatically generates visual circuit schematics, accelerates debug and helps to solve design problems in Digital Circuits, Mixed-Signal ASICs, Analog Circuits, Printed Circuit Boards and MEMS.